ApexCore A RISC-V based CPU
Designing RISC-V Single Core with IMAF extensions
Topic
Designing RISC-V Single Core with IMAF extensions
Improvise. Adaptive Control. Overcome.
Developing an EMG system that can understand human hand motions.
Implementing a RISC-V CPU on FPGA
Develop a Line following and Maze Solving bot based on the PID controller which can find the shortest path in a given maze.
To create an EMG (Electromyography) Arm Band, which may be worn as a bracelet, to detect hand movements and orientation via muscle impulses transmitted through your forearm.
Implement MPC using LQR on rotary inverted pendulum in simulation and hardware
The RISC-V CPU will be implemented with IMAF instruction extensions, and also verified using custom verification methods.
Overview of Project Soft Quad and Tasks throughout the First Week
A brief explanation on FPGAs